Wafer Acceptance Test (WAT) Parallel Parametric Tester 'PPT8200'
Achieved over 50% higher throughput compared to conventional serial testers by adopting Per-Pin architecture!
The "PPT8200" is a high-performance parallel parametric test system designed with a "Per-Pin" architecture to optimize test efficiency. Equipped with SMUs and PGUs for each pin, it achieves over 50% higher throughput compared to traditional serial testers. The advanced software environment simplifies the development of test programs. It accelerates mass production launches, supports array testing, and provides a solution that balances high reliability and cost efficiency. 【Key Specifications (Partial)】 ■ Architecture: Per-Pin Architecture ■ Number of Pins: 48 Pins ■ Configuration: Per-Pin SMU, Per-Pin PGU ■ Voltage Range: ±200V ■ Current Range: ±1A ■ Throughput: >50% improvement compared to serial testers *For more details, please download the PDF or feel free to contact us.
- Company：Yonata Electronics
- Price：Other
